1. Field of the Invention
The present invention relates generally to a path timing detection circuit and a detection method thereof. More particularly, the invention relates to a path timing detection circuit and a detection method thereof to be used for Code Division Multiple Access (CDMA) receiver device.
2. Description of the Related Art
The path timing detection circuit is for detecting an arrival timing of each signal from a transmission path (multiple paths). FIG. 15 is a diagrammatical explanatory illustration for explaining multiple paths. As shown in FIG. 15, signals transmitted to a receiver device 102 from a transmission device 101 are a signal S1 to be directly received by the receiver 102 from the transmitting device 101, a signal S2 transmitted from the transmitting device 101 and received by the receiver device 102 as reflected from a barrier 103, and a signal S3 transmitted from the transmitting device 101 and received by the receiver device 102 as reflected from a barrier 104, for example. The signals S2 and S3 from the transmitting device 101 are reflected by the barriers 103 and 104 and then reach the receiving device 102. Therefore, a timing to reach the receiving device 102 is delayed from that of the signal S1.
FIG. 16 is an explanatory illustration of a reception timing for explaining the multiple paths. In FIG. 16, an ordinate axis represents a signal level and an abscissa axis represents a time. As shown in FIG. 16, the signal S2 having the shortest transmission path next to the signal S1 is received at second, and the signal S3 having the longest transmission path is received at the last.
The path timing detection circuit according to the present invention is particularly used for determining a reception timing of a finger of RAKE receiver employed in the communication device of a CDMA system.
Such path timing detection circuit is generally realized by measuring a delay profile of the transmission path by performing correlated arithmetic operations of a reception signal and spread code using a sliding correlator or matched filter (delay line matched filter) and detecting a correlated peak position of the delayed profile. The xe2x80x9cdelayed profilexe2x80x9d means the characteristics shown in FIG. 16. Namely, the xe2x80x9cdelay profilexe2x80x9d means delay periods t1 to t3 of the signal and an average distribution of intensities V1 to V3.
Here, brief discussion will be given for xe2x80x9ccorrelated arithmetic operation of the reception signal and the spread codexe2x80x9d. FIG. 17 is a diagrammatic illustration for explaining the correlated arithmetic operation of the reception signal and the spread code. As one example, the reception data is expressed by R(n) of (n+1) in number (wherein n is positive integer) and the spread code is expressed by P(n) of (n+1) in number. Here, the reception data R(n) is a signal modulated by a predetermined spread code upon transmission. As the spread code P(n) to be used in the correlated arithmetic operation, the same code as the spread code upon transmission is used. As shown in FIG. 17, one symbol is formed with (N+1) chips.
The xe2x80x9ccorrelated arithmetic operation of the reception signal and the spread codexe2x80x9d is similar in meaning to despreading of the reception signal. Namely, in the correlated arithmetic operation, multiplication of the reception data R(0) and the spread code P(0), multiplication of the reception data R(1) and the spread code P(1) and similarly, multiplication of the reception data R(n) and the spread code P(n) are performed. Next, all of these products of multiplication are summed. Accordingly, an added value D is expressed by sum of the products of multiplication (R(0)xc3x97P(0)+R(1)xc3x97P(1)+ . . . R(n)xc3x97P(n)). The added value D represents a correlated power E of the received signal. When the correlated power E exceeds a predetermined value, the received signal is judged as the objective signal. On the other hand, the number of times of multiplication of the reception data R(n) and the spread code P(n) becomes the number of times of cumulation L (or correlation length) (namely, L=n+1).
Here, for application of a portable telephone or the like, both down-sizing lower current consumption, and higher performance associated with broadening of the band of the CDMA system are required. In order to satisfy this demand, as disclosed in Japanese Unexamined Patent Publication No. Heisei 10-190522 (hereinafter referred to as reference 1), for example, an average delay profile is generated using the matched filter and an average signal power measuring portion, a threshold value depending upon a maximum value signal power of the average profile is set, and the multiple paths exceeding the threshold value is selected as a RAKE combination object.
In the conventional correlator as disclosed in the foregoing reference i, a result of correlation resulting from correlating arithmetic operation over a predetermined correlation length (number of times of cumulation) L is output. When the level of the correlation value E as output of the correlator is high, judgment is made that the reception wave (path) is detected. The correlation length can be relatively short when the level of noise and interfering wave in the propagation environment is low.
In Japanese Unexamined Patent Publication No. Heisei 9-321663 (hereinafter referred to as reference 2), an example of a synchronization tracking device setting a correlation length L of the correlator depending upon a power of the path is disclosed. In the method disclosed in the reference 2, the correlation length L can be set shorter in relative good propagation environment and can be set longer in a relatively worse propagation environment. Therefore, path tracking can be performed at constantly stable conditions.
On the other hand, another example of the path timing detection circuits have been disclosed in Japanese Unexamined Patent Publication No. Heisei 10-94041, Japanese Unexamined Patent Publication No. Heisei 10-336072, Japanese Unexamined Patent Publication No. Heisei 10-200444 and Japanese Unexamined Patent Publication No. Heisei 10-200505.
However, with the invention disclosed in the foregoing reference 1, when the propagation environment is bad, the path buried in the noise cannot be detected unless the correlation length L is set sufficiently long. Accordingly, in order to maintain reception performance of the device, it is required to form the correlator having a long correlation length L adapting to the case of a bad propagation environment. However, wasteful arithmetic operation is inherently performed when the propagation environment is good.
On the other hand, the invention disclosed in the foregoing reference 2 is used as synchronization capturing means for maintaining synchronization for a found path instead of detecting a plurality of paths from a wide range. Therefore, means for detecting a plurality of paths have not been proposed. None of other references provides such a teaching.
An object of the present invention to provide a multiple path timing detecting circuit and a detection method thereof, which can save the amount of current consumed by omitting correlative arithmetic operation (cumulation) of an unnecessarily long correlation length L when a propagation environment is relatively good, and a plurality of paths can be detected with high precision.
According to the first aspect of the invention, a path timing detector circuit performing a correlative arithmetic operation of a spread modulation wave and a predetermined spread code with a given period of delay and detecting a reception timing of the spread modulation signal via each path on the basis of a result of the correlative arithmetic operation, comprises:
a monitoring device for monitoring whether a cumulated value exceeds a threshold value during the correlative arithmetic operation process; and
a correlative arithmetic operation controller responsive to the cumulated value in excess of the threshold value for stopping the correlative arithmetic operation in a corresponding delay period.
The correlative arithmetic operation may be performed for a plurality of times with the given period of delay. The path timing detector circuit may further comprise a holding amount for holding a number of times of cumulation at the time of stopping of the correlative arithmetic operation, and a path candidates classifying device for classifying detected candidates according to the held number of times of cumulation.
The path timing detector circuit may comprise a plurality of correlative arithmetic operation devices for performing a plurality of correlative arithmetic operations simultaneously corresponding to a plurality of delay periods. Also, the path timing detector circuit may further comprise a second correlative arithmetic operation controller for stopping arithmetic operations in all of the correlative arithmetic operation when number of cumulated values exceeding the threshold value, exceeds a predetermined number. A plurality of correlative arithmetic operation devices may be grouped to form sets per at least two, and the path timing detector circuit further includes OR devices for obtaining OR of the outputs of one set of monitoring means with respect to one set of correlative arithmetic operation devices, the correlative arithmetic operation control means stops correlative arithmetic operation by one set of correlative arithmetic operation devices on the basis of the output from the OR amount. The cumulation circuit may include an adder which overflows when the threshold value is exceeded, and the monitoring devices makes judgment that the threshold value is exceeded upon occurrence of overflow.
The path timing detector circuit may further include an average value deriving circuit for deriving an average value of number of times of cumulation of path candidate output from the path candidate classifying circuit. Furthermore, the path timing detector circuit may further comprise threshold value estimating circuit for estimating the threshold value from the output from a plurality of correlative arithmetic operation circuits.
The path timing detector circuit may further comprise a reception field intensity estimating circuit for estimating a field intensity of a reception wave on the basis of number of times of cumulation at a time where the cumulated value in the process of the correlative arithmetic operation exceeds the threshold value and an AGC coefficient of a high request reception circuit upon reception of the reception wave causing the cumulated value.
According to the second aspect of the present invention, a path timing detection method performing a correlative arithmetic operation of a spread modulation wave and a predetermined spread code with a given period of delay and detecting a reception timing of the spread modulation signal via each path on the basis of a result of the correlative arithmetic operation, comprises:
a first step of monitoring whether a cumulated value exceeds a threshold value during a process of the correlative arithmetic operation; and
a second step initiated in responsive to the cumulated value in excess of the threshold value, of stopping the correlative arithmetic operation in a corresponding delay period.
The correlative arithmetic operation may be performed for a plurality of times with the given period of delay. The path timing detector method may further comprise a third step of classifying detected candidates according to held number of times of cumulation upon stopping of the correlative arithmetic operation at the second step.